Shenzhen Integrated Circuit Industry Special Subsidy

Shenzhen Integrated Circuit Industry Special Subsidy

Supports Shenzhen integrated-circuit design through STIC subsidies for tape-out and silicon design tooling development.

The Shenzhen Integrated Circuit Industry Special Subsidy is a municipal non-repayable subsidy program administered by the Shenzhen Science, Technology and Innovation Commission (STIC-SZ) to strengthen the local IC design and manufacturing ecosystem in the context of China's semiconductor self-sufficiency drive following U.S. export controls. The program operates across three sub-tracks: IC Design Tape-out Support, which subsidizes multi-project wafer (MPW) tape-outs and first-time full-mask engineering product tape-outs; Silicon IP Purchasing Support for IC design enterprises acquiring IP for high-end chip R&D; and EDA Tool Development subsidies for companies engaged in electronic design automation tool research. Eligibility is restricted to IC design and manufacturing companies registered or operating in Shenzhen; universities, research institutes, and non-profit entities are not eligible. Applications require supporting documentation, and any fraudulent claim results in permanent blacklisting from Shenzhen municipal programs.

The program is aligned with Shenzhen's broader Hi-Tech Industrialization strategy and sits alongside related initiatives including the broader semiconductor chip subsidies (up to CNY 10M for qualifying semiconductor companies) and government rent subsidies for chip industry tenants. Award amounts per sub-track are not fixed in publicly available source materials — applicants must consult the specific annual or rolling call notice on the Shenzhen S&T Management System for exact subsidy rates and caps applicable to their tape-out geometry, IP purchase value, or EDA development scope.

For IC companies based in Shenzhen, the STIC-SZ IC subsidy is a recurring cost-offset mechanism rather than a competitive research grant. Tape-out costs — particularly for first-time full-mask runs — are the most generously subsidized sub-track, making it most relevant for early-stage fabless chip design companies completing their first silicon. The rolling structure means applications can be submitted outside fixed annual windows, though individual sub-track cycles may have their own opening periods.