Strained silicon-on-insulator substrates for 7nm FD-SOI semiconductor manufacturing
Funds one accelerator to bring strained silicon-on-insulator substrates to industrial-scale wafer production for 7nm FD-SOI chip manufacturing.
Strained silicon-on-insulator substrates for 7nm FD-SOI semiconductor manufacturing is a Chips Joint Undertaking (Chips JU) grant that funds one accelerator to bring strained silicon-on-insulator (sSOI) substrates to industrial-scale wafer production for 7nm FD-SOI chip manufacturing. The accelerator is expected to have a particular focus on complementarity with the FD-SOI pilot line, working alon…
This call funds an accelerator that develops industrial-grade strained silicon-on-insulator (sSOI) substrates and Process Design Kits, targeting readiness for high-volume 7nm FD-SOI semiconductor manufacturing by 2030. It covers strain-engineering, wafer bonding, defect reduction and process integration, plus training programmes for European technologists and engineers.
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